A sequential time base acts as a kind of pulse generator, the input to which is an external repetitive (but sometimes aperiodic) trigger signal, and the output of which is a sampling pulse that is delayed from the trigger signal by a known, programmable amount of time.
A sequential sampling time-base is a variable delay generator that receives trigger signals and generates sampling pulses. These sampling pulses are positioned at predetermined delays from a stable trigger, thereby allowing the sampling point to progress a small amount each sampling interval, and therefore over time, sample enough points on a repetitive signal to reproduce the signal. The timing delay that is to be employed must allow for a particular precise delay to be generated so that the sampling point moves uniformly through the repetitive signal.
As will be described below, methods for generating this delay have used both analog and digital techniques for obtaining high time accuracy, typically a combination of a ramp generator and a startable oscillator. However the latter is burdened with a choice between overall stability and a quick response. As a result, the jitter specification employing such a system degrades rapidly as the delay time increases.
Prior attempts at providing such a predictable delay for a sequential timebase have met with less than complete success and generally fall into three categories. As is shown in FIG. 1a, a first method employs only an analog ramp function. Thus, upon receipt of a trigger 110, an analog ramp 115 is started. When the voltage in the system reaches a predetermined level 120, resulting in a predetermined time interval, a sample is taken. By adjusting the predetermined voltage level 120, the time interval 121 generated by the ramp can be changed. Alternatively, as is also shown in FIG. 1a, the slope of the ramp may be altered (see analog ramp 116) by changing some of the components in the system, thereby altering the time interval generated by the ramp. This scheme runs into many problems as the length of time to be generated increases. To increase the time interval, the slope of the ramp is flattened. However, this flattening of the slope of the ramp introduces more substantial jitter when the ramp reaches the predetermined voltage level.
Referring next to FIG. 1b, in an attempt to generate less jitter characteristic in a sequential sampling system or a delay generator, it has been suggested to combine fine and coarse delay systems. Thus, as shown in FIG. 1b, a startable oscillator 135 is started upon receipt of trigger 110. The desired time length is counted out by clock oscillations. Additionally, after a predetermined number of clock oscillations have passed, a ramp 130 is started. This ramp allows the coarse timing based upon the counting of clock oscillations to be broken into finer divisions. Thus, by selecting a predetermined voltage level, 120, a corresponding predetermined time interval, preferably smaller than a coarse clock interval time but any appropriate precise timing interval may be employed, may be defined so that a total desired time interval is generated by counting a predetermined number of clock cycles and adding a fine timing interval on the end. This allows longer delays to be generated with less jitter introduced than that introduced due to the flattening of the ramp, as described with reference to FIG. 1a above.
The output of the startable oscillator is used as a coarse time delay for a strobe generator. The strobe generator has a digital counter that is loaded with a coarse delay value from a controller. The output of the startable oscillator is applied to the counter which increments or decrements the counter. The counter increments to a terminal count or decrements to zero whereupon a strobe pulse is generated. This strobe pulse is applied to an analog time interpolator circuit that generates the fine time interval. The controller provides a digital threshold value to a digital-to-analog converter which converts the digital value to an analog threshold value which is applied to the interpolator circuit. The strobe signal from the counter initiates the generation of a ramp signal in the interpolator circuit. The interpolator circuit generates an output strobe pulse to a sampler circuit when the ramp signal equals the analog threshold value.
However, there are a number of problems with this type of system. Indeed, U.S. Pat. No. 5,959,479 issued to Woodward, titled “Sampling Timebase System” (1999) describes that in such a sequential timebase system, the frequency stability of the startable oscillator is compromised since the startable oscillator is designed to have a quick startup time. As a result, jitter becomes larger as the time delay increases.
Another approach is to use an internal high-Q oscillator as a coarse delay clock for counting clock cycles. While this produces a stable oscillation, in order to consider non-integer time intervals, an analog ramp is used, a first portion of the ramp time being used to track timing from trigger to a predetermined oscillation of the stable clock and a second portion of the ramp being used to track timing from the end of a predetermined number of clock oscillations to a predetermined voltage threshold indicative of the desired timing interval. This configuration is described, for example, in U.S. Pat. No. 4,260,912 issued to M. D. Bjorke, titled “Digital Delay Generator” (1981) in addition to a number of other patents. Such a scheme is depicted in FIG. 1c, wherein upon receipt of a trigger 110, an analog ramp 140 is started, and continues to rise until a predetermined clock pulse 142 of a stable oscillator 141 is reached. At this time, the voltage rise in the analog ramp is stopped, and the system counts a predetermined number of clock pulses from the stable oscillator. Once this predetermined number of clock pulses has been reached (1 clock pulse in FIG. 1c) the analog ramp is started again, and rises until the analog threshold 120 is reached, thus denoting the end of the timing interval. While the timing interval is nominally the same as that shown in FIG. 1b (i.e. the timing for the number of selected clock pulses plus the timing for the analog ramp to reach the predetermined voltage level) because in FIG. 1c the oscillator can be a crystal (or crystal referenced), it therefore does not have the startup and stability problems associated with the prior arrangement described in FIG. 1b. However, while U.S. Pat. No. 4,260,912 professes a virtually jitter free timing interval, there is in fact substantial jitter produced in this arrangement because of non-linearities associated with each portion of the ramp, and there are settling time issues when the ramp is stopped and the ramp voltage is intended to be held constant. This is typically not the case.
U.S. Pat. No. 5,402,019 issued to Drummond, and titled “Phase Startable Clock Device” describes a phase startable clock device having a crystal referenced clock. The phase startable clock device generates a sinusoidal signal, the phase of which corresponds to a time difference between a trigger input and an internal clock generated time. While the name “a phase startable clock device” is similar to a conventional startable oscillator, its principal operation is almost the same as the system depicted in FIG. 1c. However, the almost instantaneous synchronization of the sinusoidal signal phase to the external triggering event is not perfect due to nonlinear effects in the analog processing circuits in the phase startable clock device. The non-ideal circuit operation translates into systematic trigger and gated clock or strobe timing delay errors. These delay errors manifest themselves as deterministic jitter at the output of the timing circuit.
U.S. Pat. No. 6,411,244 issued to Dobos et al., titled “Phase Startable Clock Device For A Digitizing Instrument Having Deterministic Phase Error Correction” (2002), U.S. Pat. No. 6,384,657 issued to Dobos et al., titled “Phase Startable Clock Device Having Improved Stability” (2002), and U.S. Pat. No. 6,522,983 issued to Dobos et al., titled “Timebase Calibration Method For An Equivalent Time Sampling Digitizing Instrument (2003) recognize the shortcomings of the above system of FIG. 1c and propose a countermeasure. For example, the '983 patent utilizes a look-up calibration table based upon only time difference information indicative of the timing between the trigger and the clock to generate a compensation table. While this approach recognizes the jitter problem inherent in the timing circuit, the proposed response is inadequate to sufficiently reduce deterministic jitter.
Therefore, it would be beneficial to provide an improved system and apparatus allowing for a more stable timebase in a sequential timebase system that sufficiently reduced deterministic jitter.